Thought on new clock design

Requirements for a new clock:

• the output of the clock is a pair of square waves. clk is a 1/4 duty cycle (i.e. high for one quarter of the cycle, low for the remaining three quarters). clk2 is a normal 1/2 duty cycle:

• on power on (or reset) the clock should run at some pre-configured speed until the reset line goes high. The speed will be whatever the ROM->RAM copying circuit can reliably sustain

• the clock must have two normal modes: running at a configurable speed, and halted

• it should be possible to switch between modes by pulling control lines low (say, clk_hlt and clk_run). If either of these is asserted when the clock is already in the appropriate mode, nothing happens. If clk_halt is asserted while the clock is in run mode, the clock must switch to the halted mode on the next rising edge of clk, so that it halts with both clocks high:

  If clk_run is asserted when the clock is halted, clk must remain high for at least 1/4 of the normal running clock cycle. In particular, we must never get a short clk pulse, even if we do something weird like pull hlt low then immediately pull run low:

• in halted mode, each negative edge on a clk_pulse line must cause the output clock(s) to advance quarter of a cycle