Sometimes you have what seems like a genius idea that comes back to bite you later. Back in 2022, when I started building the control unit, I had an idea that I thought would both prevent bus contention and simplify debugging.

Over the last few years I've run into a fair few issues with the existing design and build. Some are just the expected issues that crop up when you let an inexperienced code monkey loose on hardware, but others are a bit more architectural. So, I've decided I think it's …

A couple of days ago I managed to get the clock looking much better with some capacitors and a small smoothing resistor. So, armed with my new oscilloscope, it was time to hook it back up to the rest of the system and see how things worked.

Short answer: they …

Following on from the last investigation into the mysterious decrement bugs I decided I'd done as much debugging as I could with just my old Saleae logic analyser, and took the plunge and bought an oscilloscope. I'm surprised I've managed to get away without having one for so long.

Once …

A few months ago I was trying to track down a bug that mainly seemed to affect decrementing r1 from 255 to 0, where the register value would occasionally jump to a more-or-less random value part-way through the decrement sequence. I never did get to the bottom of it, and …

I've just finished putting together a new clock to replace the original one (which was almost a direct copy of Ben Eater's). The new one has a few nice features:

• it can generate three clock signals: the ¼-duty-cycle clock (clkq) used by the control unit, the standard ½-duty-cycle (clkh) used …

Since I added the hacked up display module, I've noticed an issue that's cropped up a few times. Since I haven't properly implemented reading the status register from the LCD controller yet, I've had to put small delay loops between character writes to avoid sending data too quickly. These are …

Following on from the CPUs first successful run a couple of weeks ago, I decided that patterns in registers are all well and good, but what it really needed was an LCD display. Since I had one in a drawer that seemed to use a Hitachi HD44780 controller, it was …

It's alive! I got the first successful run of the whole system today, booting into a simple test program that just displays a Knight Rider-like pattern on the S1 register LEDs. The only component that's not on a PCB now is the clock (which I haven't documented yet), which is …

Some quick notes on debugging the new revision of the decode card:

• plugging card in prevents reset from making any progress. With the logic analyser it's clear that rst_trig is being triggered every clock cycle. This is because there's a bug in the logic for controlling the control memory daughter …

Following on from last month's musings, over the last couple of months I've done a bit more work on the LLVM backend for the MUPS/16. Whilst implementing support for global symbols (which includes function addresses) I realised I'd made a bit of a mistake with the design of the …

I had thought the MMU was pretty solid, since I gave it a good test after its v1.1 rework, and didn't find any issues. In testing the control unit, though, I've noticed some weirdness. Mapping addresses didn't work consistently. More often than not, about half the bits were incorrect …

Notes:

• low-temperature solder paste does not flow nearly as well as original version. Maybe because it's not thermally stable, and I'm not storing it at a constant temperature?

• short between VCC and GND after assembly and soldering. Removed 48 of 60 capacitors before finding the culprit on the 49th.

• bug …

Since the first version of the μcode address generator had a few issues, I re-worked it to fix them, and while I was at it I let a bit of feature-creep happen. The 1.1 revision of the board has quite a lot more functionality than the 1.0 one …

Before testing the new control boards, all of which are driven off a single SPI EEPROM chip containing the microcode, I needed to add code to the Arduino server to read and write SPI ROMs, again - this was in the old version of the server, but not ported over.

Adding …

Random notes on things I've noticed over the last few weeks that could be improved:

I combined the PC and immediate units into one board since the immediate unit has three outputs (data, B bus, and PC), and combining the imm and PC units onto one board saved 16 lines on the backplane for the imm->PC connection. Technically, there's a LUI 'unit' here too …

It's been almost 18 months since I had any time to work on this (life got in the way), but I've started assembling and testing the last batch of boards I designed, and working on the next lot.

The μcode address generator was the simplest piece of the control unit …

Requirements for a new clock:

• the output of the clock is a pair of square waves. clk is a 1/4 duty cycle (i.e. high for one quarter of the cycle, low for the remaining three quarters). clk2 is a normal 1/2 duty cycle: