Sometimes you have what seems like a genius idea that comes back to bite you later. Back in 2022, when I started building the control unit, I had an idea that I thought would both prevent bus contention and simplify debugging.

A couple of days ago I managed to get the clock looking much better with some capacitors and a small smoothing resistor. So, armed with my new oscilloscope, it was time to hook it back up to the rest of the system and see how things worked.

Short answer: they …

Following on from the last investigation into the mysterious decrement bugs I decided I'd done as much debugging as I could with just my old Saleae logic analyser, and took the plunge and bought an oscilloscope. I'm surprised I've managed to get away without having one for so long.

Once …

I've just finished putting together a new clock to replace the original one (which was almost a direct copy of Ben Eater's). The new one has a few nice features:

• it can generate three clock signals: the ¼-duty-cycle clock (clkq) used by the control unit, the standard ½-duty-cycle (clkh) used …

Requirements for a new clock:

• the output of the clock is a pair of square waves. clk is a 1/4 duty cycle (i.e. high for one quarter of the cycle, low for the remaining three quarters). clk2 is a normal 1/2 duty cycle: