Debugging the MMU

Notes

I don't really have time to write this up properly, so these are just some notes from debugging the MMU as I go along.

20210517

• left-hand A bus connection is misplaced by X mm (too far right)
• set_tbl_index works
• set_tbl_entry mostly works? Seems to set the physical page correctly, except for the final 4 bits of the address. Short in the memory data lines? Or bad connection in the bus_a input (already broke two legs off, bits 14 and 15)
• mapping addresses doesn't work (fault is always low). Maybe not particularly surprising, given the missing connections in bus_a

20210519

• Soldering a connection for the missing pins has made things worse. set_tbl_index no longer works (sets correctly, but can't read back now)
• Removing memory board seems to have fixed that?! set_tbl_index works, and set_tbl_entry reports the correct address in all bits now (previously was wrong in the last four)
• Probe installed, problem obvious: voltages on RAMOUT and RAMWRITE are nowhere near spec. RAMWRITE high voltage is OK (4.8v), but low is about 0.7, right on the threshold. RAMOUT is just terrible: high is anything from 3.1 to 4.9v, low between 0.6 and 1.5v. Short circuit somewhere?
• Problem solved: the entire pinout on the RAM chips is wrong. Mapping matches the SOJ version of the chip, not the TSOP one. RAMOUT is connected to IO/3, and RAMWRITE to CE.