Sometimes you have what seems like a genius idea that comes back to bite you later. Back in 2022, when I started building the control unit, I had an idea that I thought would both prevent bus contention and simplify debugging.

Some quick notes on debugging the new revision of the decode card:

• plugging card in prevents reset from making any progress. With the logic analyser it's clear that rst_trig is being triggered every clock cycle. This is because there's a bug in the logic for controlling the control memory daughter …

Following on from last month's musings, over the last couple of months I've done a bit more work on the LLVM backend for the MUPS/16. Whilst implementing support for global symbols (which includes function addresses) I realised I'd made a bit of a mistake with the design of the …

Since the first version of the μcode address generator had a few issues, I re-worked it to fix them, and while I was at it I let a bit of feature-creep happen. The 1.1 revision of the board has quite a lot more functionality than the 1.0 one …

Random notes on things I've noticed over the last few weeks that could be improved:

I combined the PC and immediate units into one board since the immediate unit has three outputs (data, B bus, and PC), and combining the imm and PC units onto one board saved 16 lines on the backplane for the imm->PC connection. Technically, there's a LUI 'unit' here too …

It's been almost 18 months since I had any time to work on this (life got in the way), but I've started assembling and testing the last batch of boards I designed, and working on the next lot.

The μcode address generator was the simplest piece of the control unit …

I finally decided to stop tweaking the design of the pieces of the control unit that have been mostly complete for almost a year now, and just send them to be manufactured. There are four new boards here:

• a new lower backplane
• a new tester board to allow an Arduino …

The control lines are designed with a couple of common features:

• they all have a safe or no-op state when the lines are high. For simple lines, this means that they are active-low. For encoded lines, this means that all ones is a no-op command
• they all have pullup resistors …

I've finally had a bit of time around work to get back to this. The last major piece to do is the control unit, and since a) I expect this will take several attempts to get right, and b) I only left myself a 14x20cm space for the whole unit …

Several of the instructions in the current design need a bit of a rethink. In particular, I've been thinking about how this CPU could eventually be pipelined, and as part of that, how to simplify the control unit. I've probably made too much use of the flexibility that microcoding instructions …

I'm going to just call interrupts, syscalls, page faults, privilege errors etc. exceptions from now on to save typing. Since the current design of exceptions has a few flaws, we need a new design. I'm not keen on redesigning the existing hardware I've made if possible, so that means no …

My first attempt at implementing interrupt, syscall and exception handling in MUPS/16 currently has 4 types of traps:

• interrupts (currently 4, with equal priority)
• page faults
• syscalls
• privilege errors

Syscalls are handled slightly differently as they are completely synchronous, and so can be treated just as another instruction (R-type …